IBM unveils a stacked-transistor chip design it says can extend Moore's Law a decade
IBM has unveiled a prototype chip using a “nanostack” architecture that stacks transistors vertically in two layers, packing roughly 100 billion transistors onto a die the size of a fingernail — about double the density of its 2021 technology. The design uses complementary field-effect transistors layered like a cake, with the second layer offset rather than directly aligned to simplify wiring. Each channel is built from three nanosheets about 15 atoms thick.
Compared with its previous generation, IBM says the nanostack does about 50% more computation in the same time and is up to 70% more energy efficient. Jay Gambetta, who directs IBM Research, called it “a meaningful leap forward,” and analyst Dan Hutcheson of TechInsights said it “puts another ten, fifteen years on the roadmap.”
The significance is less about any single chip than about direction. Transistors are nearing a physical floor where shrinking them further invites quantum interference, which has slowed the steady density gains the industry has relied on for decades. Stacking is a way to keep increasing transistor counts without making individual devices smaller. IBM does not manufacture leading-edge chips at volume itself; it expects to license the technique to partners such as Intel, Samsung and TSMC, with data-center deployment anticipated within roughly a decade — so the commercial payoff, if it materializes, is years out.